The invention relates generally to a method for fabricating a semiconductor device, and more specifically, to a method for performing a fracturing process by adding a subsidiary pattern to divide a region excluding a mask pattern.
In the case of semiconductor devices such as DRAM, a technique is required to add additional transistors in a limited region to improve integration. Accordingly, a vertical transistor as an element included in high integrated memory cells generally having an area of 4F2 has been suggested. The vertical transistor provides a surrounding gate structure that surrounds a vertical channel.
In order to form the surrounding gate in an area of 4F2, a channel region is selectively, isotropically-etched so that the channel region is formed to be thinner than source/drain regions, thereby obtaining excellent device characteristics. As a result, the vertical transistor can use the limited space more efficiently. The vertical transistor has been highlighted as a transistor for use in various applications such as DRAM where fabricating smaller transistors is optimal.
The vertical transistor is an effective means to improve a short channel effect because a given channel length can be maintained even in a reduced device area. Particularly, the surrounding gate can maximize controllability of the gate, thereby improving the short channel effect and providing excellent operating current characteristics because the current flowing area is broad. As a result, in order to increase the integration, the vertical transistor requires a thinner and longer structure.
In the memory cell having a Critical Dimension (CD) of less than 50 nm, the width of the CD of a pillar of the vertical transistor is narrow, so that it is difficult to fabricate a mask that defines the CD of the pillar.
FIG. 1 is a top view illustrating a conventional mask.
Referring to FIG. 1, a pillar pattern 20 is formed over a mask 10 including a transparent substrate 15. After forming a chrome layer over the transparent substrate 15, the pillar pattern 20 is obtained by removing a portion of the chrome layer by irradiation with electric beams into a region of the chrome layer excluding the pillar-pattern-expected region. This process is called a fracturing process. However, the CD uniformity of the pillar pattern 20 is remarkably reduced due to high-integration of semiconductor devices.
FIG. 2 is a top view illustrating a conventional method of fabricating a mask.
Referring to FIG. 2, divisional regions are numbered in order of the fracturing processes. The divisional region “1”, the divisional region “2”, the divisional region “3”, and the divisional region “4” each have different shapes, which results in each having a different irradiation degree of E-Beam. As a result, the uniformity of the pillar pattern 20 is reduced.
Specifically, E-Beam is irradiated once on the left and right sides of the divisional region “2” of the chrome pattern element A. However, E-Beam is irradiated twice on the left and right sides, respectively, of the divisional region “2” of the chrome pattern element B. As a result, the lithography number is different in the peripheral divisional regions of the chrome pattern element A and the chrome pattern element B.
As a result, the non-uniformity of the pattern is generated by a difference in sizes of the divisional regions.
FIGS. 3 and 4 are micrographs illustrating defects of a semiconductor device formed using a conventional mask.
Referring to FIGS. 3 and 4, a photoresist pattern formed using a mask having reduced uniformity as shown in FIG. 2 shows multiple occurrences of a defect, that is, a bridge phenomenon between the photoresist patterns.
FIG. 5 is a simulation diagram illustrating the CD non-uniformity of the semiconductor device formed using the conventional mask.
Referring to FIG. 5, the diagram shows that the color is differentiated in each CD of the pillar pattern formed over the mask. A CD of the pillar pattern is changed depending on the exposed region.
FIG. 6 is a graph illustrating CD non-uniformity of a conventional mask.
Referring to FIG. 6, the graph shows the simulation results of FIG. 5 and compares the change in the CD of the pillar pattern 20 depending on locations of the pillar pattern 20 formed over the mask.
As mentioned above, when the divisional regions of the fracturing process are defined differently in formation of a mask for manufacturing a semiconductor device, the uniformity of the mask pattern that defines the semiconductor device is reduced. As a result, when a semiconductor device is manufactured with a mask having non-uniformity, defective patterns are generated, thereby degrading yield and reliability of the semiconductor device.